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features monolithic cmos a/d converters microprocessor compatible parallel and serial output inherent track/hold input true 12, 14 and 16-bit precision conversion times: cs501 6 16.25 m s cs501 4 14.25 m s cs5012a 7.20 m s self calibration maintains accuracy over time and temperature low power dissipation: 15 0 mw low distortion general description the cs5012a/14/1 6 are 12, 14 and 16-bit monolithic analo g t o digital converters wit h conversion times of 7.2 m s, 14.25 m s and 16.25 m s. unique self-calibration cir- cuitry insures excellent linearity and differential non- linearity , with n o missing codes . offset and full scale errors are kept within 1/2 lsb (cs5012a/14) and 1 lsb (cs5016), eliminatin g the need for calibration. unipolar an d bipolar input ranges are digitally select- able. the pin compatible cs5012a/14/16 consist o f a dac, conversion and calibration microcontroller, oscillator, comparator, microprocessor compatible 3-state i/o, an d calibration circuitry. the input track-and-hold, in- herent t o the devices sampling architecture , acquires th e input signal after each conversion using a fast slewing on-chip buffer amplifier. this allows throughput rate s up to 10 0 khz (cs5012a), 56 khz (cs5014) and 50 khz (cs5016). an evaluation board (cdb5012/14/16) is available which allows fast evaluation o f ad c performance. ordering information: pages 2-45, 2-46, & 2-47 ja n ' 01 ds14f7 2-7 crystal semiconductor corporation p.o. box 17847, austin, tx 78760 (512) 445 7222 fax: (512) 445 7581 16, 14 & 12-bit, self-calibrating a/d converters semiconductor corporation cs5016 cs5014 cs5012a d5 d6 d7 d8 d9 d 1 0 d 1 1 d 1 2 d 1 3 d 1 4 d 15 (m s b) d 4 ( l s b) c s 5 0 1 2 a 6 7 8 9 12 13 14 15 16 17 18 19 d2 ( ls b ) c s 50 1 4 d0 ( ls b ) c s 50 1 6 d1 sc l k e o t e o c s d ata 2 3 4 5 3 7 38 39 40 d3 c l kin c l o c k g e n e r a tor 20 i n t r l v 34 r s t 32 21 a0 23 rd 22 h o ld 1 bw 33 24 c a l 35 cs b p / u p ref b u f a g nd 29 v r e f 28 a i n 26 27 c h a r ge r e d i s t r i b u t i o n d a c c o m par a t or va+ v a- v d + vd- dgnd t s t 25 30 1 1 3 6 10 3 1 + - + - + - + - co n trol c a l i b r a t i on me m o r y m i c ro c on t ro l l e r sta t us r e g i ster copyright ? crystal semiconductor corporation 1995 (all rights reserved)
c s 5 0 1 2 a cs5012a analog characteristics ( t a = t m i n t o t m a x ; v a +, vd + = 5 v ; v a -, vd - = - 5v; vr e f = 2.5v to 4.5 v ; f clk = 6. 4 mhz for -7 , 4 mhz for -12; analog source impedance = 20 0 w ) cs5012a-b parameter* min typ max units specified temperature range -4 0 to +85 c accuracy linearity error (not e 1) drift (note 2) 1/4 1/8 1/2 lsb 12 d lsb 12 differential linearity (note 1) drift (note 2) 1/4 1/32 1/2 lsb 12 d lsb 12 full scal e e rror (note 1) drift (note 2) 1/4 1/16 1/2 lsb 12 d lsb 12 unipolar offset (note 1) drift (note 2) 1/4 1/16 1/2 lsb 12 d lsb 12 bipolar offset (not e 1) drift (note 2) 1/4 1/16 1/2 lsb 12 d lsb 12 bipolar negative full- s cal e erro r (not e 1) drift (note 2) 1/4 1/16 1/2 lsb 12 d lsb 12 total unadjusted error (note 1) drift (note 2) 1/4 1/4 lsb 12 d lsb 12 dynamic performance (bipolar mode) peak harmonic or (note 1) spurious noise full s cale , 1 kh z input full s cale , 12 kh z input 84 84 92 88 db db total harmonic distortion 0.008 % signal-to-noise ratio (not e 1) 1 khz, 0 db input 1 khz, -60 db input 72 73 13 db db noise (note 3) unipolar mode bipolar mode 45 90 m v rms m v rms notes : 1 . applies after calibratio n at any temperatur e within th e specified temperatur e range. 2 . total drift over specified temperatur e rang e since calibratio n at power-u p at 2 5 c 3 . wideband noise aliased int o the baseband . referred t o the input. * refer to parameter definitions (immediately following the pin descriptions at the end of this data sheet). specifications are subjec t to change withou t notice. 2-8 ds14f 7
cs5012a analog characteristics (continued) cs5012a-b parameter* min typ max units specified temperature range -4 0 to +85 c analog input aperture time 25 ns aperture jitter 100 ps input capacitance (not e 4) unipolar mod e cs5012a bipolar mode cs5012a 103 72 137 96 pf pf pf pf conversion & throughput conversion time -7 (notes 5 and 6) 7.2 m s acquisition time -7 (note 6) 2.5 2.8 m s throughput -7 (note 6) 100 khz power supplies dc power supply currents (not e 7) i a + i a - d + (cs5012a) i d + i d - 12 -12 3 6 -3 19 -19 6 7.5 -6 ma ma ma ma ma power dissipation (note 7) 150 250 mw power s upply rejection (note 8) po s i t i ve supp li es negative s upplies 84 84 db db notes : 4 . applies only i n trac k mode. w hen converting or calibrating , input capacitance wil l not excee d 1 5 pf. 5 . measured from fallin g transition on hold t o falling transitio n on eoc. 6 . conversion, acquisition , and throughput times depen d on clkin, sampling, an d calibratio n conditions. the numbers show n assume sampling an d conversion is synchronized wit h the cs5012 a /14/1 6 s conversion clock, interleav e calibrate is disabled, an d operatio n i s fro m the full-rated , external clock. refer to th e section conversion time/throughput for a detailed discussion of conversion timing. 7 . al l output s unloaded. a ll inputs cmos levels. 8 . with 30 0 mv p-p, 1 khz rippl e applied t o eac h analog supply separately in bipolar mode . rejection improves by 6 db i n the unipolar mod e to 9 0 db. figur e 13 shows a plo t of typica l power supply rejection versu s frequency. c s 5 0 1 2 a ds14f7 2-9
cs5014 analog characteristics ( t a = t m i n t o t m a x ; v a +, vd + = 5 v ; va-, vd- = -5v; vref = 4.5v; clkin = 4 mh z for -14 , 2 mhz for -28; analog source impedance = 20 0 w ) cs5014-b parameter* min typ max units specified temperature range -4 0 to +85 c accuracy linearity error (not e 1) drift (note 2) 1/4 1/8 1/2 lsb 14 lsb 14 d lsb 14 differential linearity (note 1) drift (note 2) 1/4 1/32 1/2 lsb 14 d lsb 14 full scal e e rror (note 1) drift (note 2) 1/2 1/4 1 lsb 14 d lsb 14 unipolar offset (not e 1) drift (note 2) 1/4 1/4 3/4 lsb 14 lsb 14 d lsb 14 bipolar offset (not e 1) drift (note 2) 1/4 1/2 3/4 lsb 14 lsb 14 d lsb 14 bipolar negative full- s cal e erro r (not e 1) drift (note 2) 1/2 1/4 1 lsb 14 lsb 14 d lsb 14 total unadjusted error (note 1) drift (note 2) 1 1 lsb 14 d lsb 14 dynamic performance (bipolar mode) peak harmonic or (note 1) spurious noise ful l s cale, 1 khz input ful l s cale, 1 2 khz input 94 84 98 87 db db db db total harmonic distortion 0.003 % signal-to-noise ratio (note s 1 an d 9) 1 khz, 0 db input 1 khz, -60 db input 82 84 23 db db db noise (note 3) unipolar mode bipolar mode 45 90 m v rms m v rms notes : 9 . a detaile d plot o f s/(n+d) vs . input amplitud e appears i n figure 2 6 for the cs5014 an d figure 28 for th e cs5016. * refer to parameter definitions (immediately following the pin descriptions at the end of this data sheet). specifications are subjec t to change withou t notice. c s 5 0 14 2-10 ds14f 7
c s 5 0 14 cs5014 analog characteristics (continued) cs5014-b parameter* min typ max units specified temperature range -4 0 to +85 c analog input aperture time 25 ns aperture jitter 100 ps input capacitance (not e 4) unipolar mode bipolar mode 275 165 375 220 pf pf conversion & throughput conversion time -1 4 (notes 5 and 6) 14.25 m s acquisition time -14 (note 6) 3.0 3.75 m s throughput -14 (note 6) 55.6 khz power supplies dc power supply currents (not e 7) i a + i a - i d + i d - 9 -9 3 -3 19 -19 6 -6 ma ma ma ma power dissipation (note 7) 120 250 mw power s upply rejection (note 8) po s i t i ve supp li es negative s upplies 84 84 db db ds14f7 2-11
c s 5 0 16 cs5016 analog characteristics ( t a = t m i n t o t m a x ; v a +, vd + = 5 v ; va-, vd- = -5v; vref = 4.5v; clkin = 4 mh z for -16 , 2 mhz for -32; analog source impedance = 20 0 w ; synchronous sampling.) cs5016-j , k cs5016-a, b cs5016-s, t parameter* min typ max min typ max min typ max units specified temperature range 0 to +70 -4 0 to +85 -55 t o +125 c accuracy linearity error j, a, s (not e 1) k, b, t drift (note 2) 0.002 0.001 1/4 0.003 0.0015 0.002 0.001 1/4 0.003 0.0015 0.002 0.001 1/4 0.0076 0.0015 % f s % f s d lsb 16 differential linearity (note 10) 16 16 16 bits ful l scale e rror j, a , s (not e 1) k, b, t drift (note 2) 2 2 1 3 3 2 2 1 3 3 2 2 2 4 3 lsb 16 lsb 16 d lsb 16 unipolar offset j, a, s (not e 1) k, b, t drift (note 2) 1 1 1 2 3/2 1 1 1 3 3 1 1 2 4 3 lsb 16 lsb 16 d lsb 16 bipolar offset j, a, s (not e 1) k, b, t drift (note 2) 1 1 1 2 3/2 1 1 2 2 2 1 1 2 4 2 lsb 16 lsb 16 d lsb 16 bipolar negative full- s cal e erro r (not e 1) j, a, s k, b, t drift (note 2) 2 2 1 3 3 2 2 2 3 3 2 2 2 5 3 lsb 16 lsb 16 d lsb 16 dynamic performance (bipolar mode) peak harmonic or (note 1) spurious noise ful l s cale, 1 khz input j, a, s k, b, t ful l s cale, 1 2 khz input j, a, s k, b, t 96 100 85 85 100 104 88 91 96 100 85 85 100 104 88 91 92 100 82 85 100 104 88 91 db db db db total harmonic distortion j, a, s ful l s cale, 1 khz input k, b, t 0.002 0.001 0.002 0.001 0.002 0.001 % % signal-to-noise ratio (note s 1 an d 9) 1 khz, 0 db input j, a, s k, b, t 1 khz, -60 db input j , a , s k, b, t 87 90 90 92 30 32 87 90 90 92 30 32 84 90 90 92 30 32 db db db db noise (note 3) unipolar mode bipolar mode 35 70 35 70 35 70 m v rms m v rms notes : 10 . minimu m resolution for which n o missing codes is guaranteed * refer to parameter definitions (immediately following the pin descriptions at the end of this data sheet). specifications are subjec t to change withou t notice. 2-12 ds14f 7
c s 5 0 16 cs5016 analog characteristics (continued) cs5016-j , k cs5016-a, b cs5016-s, t parameter* min typ max min typ max min typ max units specified temperature range 0 to +70 -4 0 to +85 -55 t o +125 c analog input aperture time 25 25 25 ns aperture jitter 100 100 100 ps input capacitance (not e 4) unipolar mode bipolar mode 275 165 375 220 275 165 375 220 275 165 375 220 pf pf conversion & throughput conversion time -1 6 (notes 5 and 6) -32 16.25 32.5 16.25 32.5 16.25 32.5 m s m s acquisition time -16 (note 6) -32 3.0 4.5 3.75 5.25 3.0 4.5 3.75 5.25 3.0 4.5 3.75 5.25 m s m s throughput -16 (note 6) -32 50 26.5 50 26.5 50 26.5 khz khz power supplies dc power supply currents (not e 7) i a + i a - i d + i d - 9 -9 3 -3 19 -19 6 -6 9 -9 3 -3 19 -19 6 -6 9 -9 3 -3 19 -19 6 -6 ma ma ma ma power dissipation (note 7) 120 250 120 250 120 250 mw power s upply rejection (note 8) po s i t i ve supp li es negative s upplies 84 84 84 84 84 84 db db ds14f7 2-13
switching characteristics (t a = t m i n t o t m a x ; v a +, vd + = 5 v 10%; v a -, vd - = - 5v 10%; inputs: logi c 0 = 0v, logic 1 = vd+; c l = 5 0 pf , b w = vd+) parameter symbol min typ max units cs5012a clkin frequency: internally generated: e xternally supplied: -7 f clk 1.75 100 khz - - - 6.4 mhz mhz cs5014/5016 clkin frequency: internally generated: -14, -16 -14, -32 e xternally supplied: -14, -16 -14, -32 f clk 1.75 1 100 khz 100 khz - - - - - - 4 2 mhz mhz mhz mhz clkin duty cycle 40 - 60 % rise times: a ny digita l input any digita l output t rise - - - 20 1.0 - m s ns fall times: a ny digita l input any digita l output t fa l l - - - 20 1.0 - m s ns hold puls e w idth t hpw 1/f clk +50 - t c ns conversion time: cs5012a cs5014 cs5016 t c 49/f clk +50 57/f clk 65/f clk - - - 53/f clk +235 61/f clk +235 69/f clk +235 ns ns ns data delay time t dd - 4 0 100 ns eo c pulse width (note 11) t epw 4/f clk -20 - - ns se t up times: cal, intrlv to cs low a0 to cs and rd low t cs t as 20 20 10 10 - - ns ns hold times: cs or rd hig h to a0 invalid cs hig h to cal, intrlv invalid t ah t ch 50 50 30 30 - - ns ns access times: cs low t o data valid a, b, j, k s, t rd lo w to dat a valid a, b, j, k s, t t ca t ra - - - - 90 115 90 90 120 150 120 150 ns ns ns ns output float delay: k, b cs or rd hig h to output hi-z t t fd - - 90 90 110 140 ns ns seria l clock p ulse width low p ulse width high t pwl t pwh - - 2/f clk 2/f clk - - ns ns set u p times: sdata t o sclk rising t ss 2/f clk -50 2/f clk - n s hold times: scl k risin g to sdata t sh 2/f clk -100 2/f clk - n s notes : 11. eo c remains lo w 4 clkin cycles if cs and rd are hel d low. otherwise, i t returns high withi n 4 clkin cycles fro m the star t of a data read operation or a conversion cycle. cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-14 ds14f 7
90% 10% t f a ll r i se t 90% 10% h i -z h i -z ch t t cs t ah t fd t as t ra t ca h o ld eoc o utput d ata t hpw t c l a st c o n v e r si o n d a ta v a l id t dd n e w d a t a v a l i d t epw d0 - d 15 a0 cs rd cal , i ntrlv s d a t a t ss t sh s c lk t p w l t pwh rise and fal l times conversion timing serial output timing read and calibration contro l timing cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-15
cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 digital characteristics (t a = t m i n t o t max ; va+, vd+ = 5v 10%; v a -, vd - = - 5v 10%) parameter symbol min typ max units high-level inpu t voltage v ih 2.0 - - v low-level inpu t voltage v il - - 0 . 8 v high-level output voltage (not e 12) v oh ( vd + ) - 1.0v - - v low-level output voltage i out = 1.6ma v ol - - 0 . 4 v input leakage current i in - - 1 0 m a 3-state leakage current i oz - - 10 m a digital output pin capacitance c out -9 - p f notes : 12 . i out = -10 0 m a . this specification guarantees ttl compatibility (v oh = 2.4v @ i out = -4 0 m a). recommended operating conditions (agnd, dgnd = 0v, see not e 13) parameter symbol min typ max units dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- v a + v a - 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 v a + -5.5 5.5 -5.5 v v v v analo g reference voltage vref 2.5 4.5 (va+) - 0.5 v analog inpu t voltage: (note 14) unipolar b ipolar v ain v ain a g nd - v ref - - vref vref v v notes : 13 . all voltages with respect t o ground. 14 . th e cs5012a/14/16 can accep t input voltage s up t o the analo g supplies (va+ and va-). i t will outpu t all 1s for inputs above vr e f an d all 0s for inputs belo w a gnd i n unipolar mode and -vref in bipolar mode. absolute maximum ratings (agnd, dgnd = 0v, al l voltages wit h repect t o ground.) warning : operatio n at or beyond these limits may reult i n permanen t damage t o the device. normal operation is no t guarantee d at these extremes. parameter symbol min max units dc power supplies: positive digital (not e 15) negative digital p ositive a nalog negative analog vd+ vd- v a + v a - -0.3 0.3 -0.3 0.3 6.0 -6.0 6.0 -6.0 v v v v input current , any pin except supplies (not e 16) i in - 10 ma analo g input voltage (ai n and vref pins) v ina (va - ) - 0.3 (va + ) + 0.3 v digital inpu t voltage v ind -0.3 (va+) + 0.3 v ambient operatin g temperature t a -55 125 c storage temperature t s t g -65 150 c notes : 15 . in addition , vd+ should no t be greater than (va+) + 0.3v. 16 . transient currents of u p to 10 0 ma wil l not caus e sc r latch-up. 2-16 ds14f 7
theory of operation the cs5012a/14/16 family utilize a success i v e ap p r o ximation c o n version tec h ni q ue. t h e a n al o g input is success i v ely compared to the output of a d/a c o n verter co n tr o lled by the c o n version al g o- rithm. success i v e approximation b e gins by comparing the analog input to the d a c output which is set to half-scale (msb on, all other bits o f f). if the input is found to be bel o w half-scale, the msb is reset to zero and the input is com- pared to one - qua r te r sc a le ( n e xt msb on, a ll others o f f). if the input were ab o v e half-scale, the msb w ould remain high and the n e xt compari- son would be at three-quarters of full scale. this procedure continues until all bits h a v e been e x er- cised. a unique cha r ge redistri b ution a r c hit e ctur e is used to implement the success i v e approximation algorithm. instead of the traditional resistor net- w ork, the d a c is an array of binary-w e ighted capacitors. all capacitors in the array share a common node at the comparator s input. their other terminals are capable of being connected to ain, a gnd, or vref (figure 1). when the d e - vice is not calibrating or co n v erting, all capacitors are tied to ain forming c tot . switch s1 is closed and the cha r ge on the arra y , q in , tracks the input signal v in (figu r e 2 a ). when the co n v ersion command is issued, switch s1 opens as sh o wn in figu r e 2 b . t h is t r aps cha r g e q in on t h e c o mparator si d e of t h e capaci- t or array and creates a floating node at the comparator s input. the co n v ersion algorithm op- erates on this f i x e d cha r ge, and the signal at the analog input pin is ignored. in e f fect, the entire d a c capacitor array ser v es as analog memory a i n vref ag n d c c / 2 c / 4 c / 8 m s b l s b bit 11 b it 10 b i t 9 bit 8 b i t 0 dummy c/x s1 bit 13 b i t 15 bi t 12 bi t 14 b i t 1 1 b i t 1 3 bit 10 bit 12 c s 5 0 1 2 a: c s50 1 4 : c s50 1 6 : c / x x = 2 0 48 x = 8 1 92 x = 32768 c s 50 1 2a cs 5 014 cs 5 016 c = c + c / 2 + c/ 4 + . . . + c/x t o t figure 1 . charge redistribution dac (1-d ) c tot in q + - v fn to mcu s1 c tot d . vref agnd d for vref v in = 0 v fn v = figure 2b. convert m ode in q c tot s1 v in a i n + - to m cu = v in c to t in -q figure 2 a . tracking m o de cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-17
during co n v ersion much li k e a hold capacitor in a sample/hold ampli f ie r . the co n v ersion consists of manipulating the free plates of the capacitor array to vref and a gnd to form a capacit i v e d i vide r . since the cha r ge at the floating node remains f ixed, the v oltage a t that point depends on the proportion of capaci- tance tied to vref versus a gnd. the success i v e-approximation algorithm is u s ed to f ind the proportion of capacitance, termed d in figur e 2b, w hi c h w h e n c onn e ct e d to th e r e f e r - ence will dr i v e the v oltage at the floating node (v fn ) to zero. that binary fraction of capacitance represents the co n v erter s digital output. this cha r ge redistri b ution architecture easily sup- ports bipolar input ranges. if half the capacitor array (the msb capacitor) is tied to vref rather than ain in the track mode, the input range is doubled and is o f fset half-scale. the magnitude o f th e r e f e r e n c e v olt a g e thus d e f ines both posit i v e and n e gat i v e full-scale (-vref to +vref), and the digital code is an o f fset binary representation of the input. calibration the ability of the cs5012a/14/16 to co n v ert ac- curately clearly depends on the accura c y of their comparator and d a c. the cs5012a/14/16 util- ize an "auto-zeroing" scheme to null erro r s introduced by the comparato r . all o f fsets a r e stored on the capacitor array while in the track mode and are e f fect i v ely subtracted from the in- put signal when a co n v ersion is initiated. aut o -zeroi n g e n hances p o wer s u p p ly rejection at frequencies well bel o w the co n v ersion rate. t o achi e v e complete accura c y from the d a c , the cs 5 0 1 2a/1 4 /16 use a no v el self-calibration scheme. each bit capacito r , sh o wn in figure 1, actually consists of s e v eral capacitors which can be manipulated to adjust the o v erall bit weight. an on-chip microcontroller adjusts the subarrays to precisely ratio the bits. each bit is adjusted to just balance the sum of all less signi f icant bits plus on e dummy lsb ( f o r e xample, 16c = 8c + 4c + 2c + c + c). calibration resolution fo r the array is a small fraction of an lsb resulting in nearly ideal di f ferential and int e gral linearit y . digital circuit connections the cs5012a/14/16 can be applied in a wide v a- riety of master clock, sampling, and calibration conditions which directly a f fect the d e vices con- v ersion time and throughput. the d e vices also f e atur e on- c hip 3 - stat e output b u f f e rs and a com- plete interface for connecting to 8-bit and 16-bit digital systems. output data is also a v ailable in serial format. master clock the cs5012a/14/16 operate from a master clock (clkin) which can be e xternally supplied or in- ternally generated. the internal oscillator is act i v ated by e xternally tying the clkin input l o w . alternat i vel y , the cs5012a/14/16 can be synchronized to the e xte r n a l syst e m by d r i ving th e clk i n pin w ith a ttl o r cmos c lo c k sig- n a l. c l k i n m a s t e r c l o c k ( o p t i on a l) hold e o t c s5 0 12a/ 1 4/ 1 6 figure 3b. synchronou s sampling c l k i n m a s t e r c l o c k (op t i o n a l) hold samp l i n g cl o c k c s 5 0 1 2 a /14/16 figure 3a. asynchronous sampling cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-18 ds14f 7
all calibration, co n v ersion, and throughput times directly scale to clkin frequen c y . thus, throughput c an b e p r e c isely cont r oll e d a nd/or maximized using an e xternal clkin signal. in contrast, the cs5012a/14/16 s internal oscillator will v ary from unit-to-unit and o v er temperature. the cs5012a/14/16 c a n typi c ally co n v e r t with c l kin as l o w as 10 khz at r o om tem p erat u re. initiating conversions a falling transition on the hold pin places the input in the hold mode and initiates a co n v ersion c ycle. upon completion of the co n v ersion c ycle, the cs5012a/14/16 automatically return to the track mode. in contrast to systems with separate track-and-holds and a/d co n v erters, a sampling clock can simply be connected to the hold in- put (figure 3a). the duty c ycle of this clock is not critical. it need only remain l o w at least one clki n c ycle plus 50 ns, b u t no longer than the minimum co n v ersion time or an additional con- v ersion c ycle will be initiated with inadequate time for acquisition. microprocessor-controlled operation sampling and c o n v e rsion c an b e pl a c e d under microprocessor control (figure 4) by simply gat- ing the d e vices decoded address with the write stro b e f o r the hold input. thus, a write c ycle to the cs5012a/14/16 s base address will initiate a co n v ersion. h o w e v e r , the write c ycle must be to the odd address (a0 high) to a v oid initiating a s o ftware c o ntrolled reset (see reset bel o w). the calibration control inputs, cal, and intr l v are inputs to a set of transparent latches. these signals are internally latched by cs return- ing high. th e y must be in the appropriate state when e v er the chip is selected during a read or write c ycle. address lines a1 and a2 are sh o wn connected to cal and intr l v in figur e 4 pla c - ing calibration under microproc e sso r cont r ol a s w ell. t h us, any read or write c ycle to the cs5012a/14/16 s base address will initiate or ter- minate calibration. alternat i v el y , a0, intr l v, and cal may be connected to the microproces- sor data b us. conversion time/throughput upon completing a co n v ersion c ycle and return- ing to the track mod e , the cs5012 a /14/16 require time to acquire the a n a log input sign a l before another co n v ersion can be initiated. the acquisition time is speci f ied as six clkin c ycles plus 2.25 m s ( 1 . 3 2 m s f o r the cs5 0 1 2 a -7 versi o n only). this adds to the co n v ersion time to de f ine the co n verter s maximum throughput. the con- v ersion time of the cs5012a/14/16, in turn, depends on the sampling, calibration, and clkin conditions. hold cs5012a/14/16 addr dec a3 an address bus wr rd cs rd intrlv a2 a1 cal a 0 a0 addr valid figure 4b. conversions unde r microprocessor control cs5012a/14/16 cs addr dec a3 an address bus rd rd conclk hold intrlv cal a0 a2 a1 a0 addr valid f igu r e 4a. conve r sions asyn c hronous to clkin cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-19
asynchronous sampling the cs5012a/14/16 internally operat e f r om a clock which is delayed and d i vided d o wn from clkin (f clk /4). if sampling is not synchronized to this internal clock, the co n v ersion c ycle may not b e gin until up to four clock c ycles after h o l d goes l o w e ven though the c ha r ge is trapped immediatel y . in this asynchronous mode (figure 3a), the four clock c ycles add to the mini- mum 49, 57 and 65 c lo c k c ycl e s ( f o r the cs5012a/14/16 respect i v ely) to de f i ne the maxi- mum co n v ersion time (see figure 5a and t a bl e 1). synchronous sampling t o achi e v e maximum throughput, sampling can be synchronized with the internal co n v er s i on clock b y c o n n ecting t h e e n d-of- t rack ( e o t) out- put to hold (figu r e 3b ) . th e e o t output falls 1 5 clkin c y cles after eoc indicating the ana- log input h a s b e en a c quir e d to the cs5012a/14/16 s sp e ci f ied a c cur a c y . th e e o t output is synchronized to the internal co n v ersion clock, so th e fou r clock c y c le syn c h r oniz a tion un- certainty is rem o ved yielding throughput at [1/64]f clk for the cs5012a, [1/72 ] f clk for cs5014 and [ 1/80 ] f clk for cs5016 where f clk is th e clkin f r equ e n c y (s e e figu r e 5b and t a - bl e 1). * c onversion (49 + n cy c les) 1 / th r o ughput (64 + n cyc l es) output eot output eoc i n p ut h o l d ac q ui s it i on ( 1 5 c yc l e s) * da s h e d l i n e : cs & rd = 0 cs5 0 1 2 a n = 0 s o l i d l i n e : se e f i g ur e 9 cs 5 0 1 4 n = 8 cs5 0 16 n = 1 6 figure 5b . synchronou s (loopback mode) con v ersion s y nchroniz a tion uncertainty (4 c y c l e s ) in p ut output output acqui s ition ho l d e o c eot 1 / thro u g hput figure 5a. asynchronous sampling (externa l clock) throughput tim e conversion time sampling mode synchronous (loopback) asynchronous min 6 4 t clk n/a n/a max 6 4 t clk 59 1.32 m s t clk + 59 2.2 5 m s t clk + max + 235 n s 5 3 t clk 4 9 t clk + 235 n s 5 3 t clk min 4 9 t clk 4 9 t clk 4 9 t clk -7 -12,-24 cs5012a cs5014 5 7 t clk 5 7 t clk + 235 n s 6 1 t clk 5 7 t clk 7 2 t clk n/a 7 2 t clk 67 2.2 5 m s t clk + synchronous (loopback) asynchronous 6 5 t clk 6 5 t clk + 235 n s 6 9 t clk 6 5 t clk 8 0 t clk n/a 8 0 t clk 75 2.2 5 m s t clk + synchronous (loopback) asynchronous cs5016 tabl e 1. conversion and throughput time s (t c l k = master cloc k period) cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-20 ds14f 7
also, the cs5012a/14/16 s internal rc oscillator exhibits jitter (typically 0.05% of its period), which is high compared to crystal oscillators. if th e cs5012a/14/16 is c on f igu r ed for syn c h r o - nous sampling while operating from its internal oscillato r , this jitter will directly a f fect sampling purit y . the user can obtain best sampling purity while synchronously sampling by using an e x ter- n a l c rystal - b a sed c lo c k. re s et upon p o w e r up, th e cs5012 a /14/16 must b e r e - set to guarantee a consistent starting condition and initially calibrate the d e vices. due to the cs5012a/14/16 s l o w p o w e r dissip a tion a nd l o w temperature drift, no w arm-up time is r equi r ed before reset to accommodate a n y self-heating ef- fects. h o w e v e r , the v olt a g e r e f e r e n c e input should h a v e stabilized to within 5%, 1% or 0.25% of its f inal v alue, for the cs5012a/14/16 respect i v el y , before rst f alls to guarantee an ac- curate calibration. late r , the cs5012a/14/16 may be reset at a n y time to initiate a single full cali- bration. reset o verrides all other functions. if reset, the cs5012a/14/16 will clear and initiate a n e w calibration c ycle mid-co n v ersion or mid-cali- b r ation. resets can be initiated in hard w are or soft w are. the simplest method of resetting the cs5012a/14/16 i n v olves strobing the rst pin high f o r at l e ast 100 ns. when rs t is b r ought high all internal logic clears. when it returns l o w , a full calibration b e gins which takes 58,280 clkin c ycles for the cs5012a (approximately 9. 1 ms with a 6. 4 mhz clock ) and 1,441,020 clkin c ycles for the cs5016, cs5014 and cs5012 (approximately 360 ms with a 4 mhz clkin). a simple p o we r -on reset circuit can be b uilt using a resisto r and c apa c ito r , and a schmitt-trigger i n v erter to pr e v ent oscillation (see figure 6). the cs5012a/14/16 can also be reset in s o ftware w h en u n d er micr o process o r co n tr o l. the cs5012a/14/16 will reset when e v er cs, a0, and hold are taken l o w simultaneousl y . see the mic r op r ocessor interfac e section (bel o w) to eliminate the possibility of inad v ertent software reset. the eoc output remains high throughout the calibration operation and will f all upon its completion. it can thus be used to generate an interrupt indicating the cs5012a/14/16 is ready for operation. while calibrating, the h o l d input is ignored until eoc f alls. after eoc f alls, six clkin c ycles plus 2.25 m s (1.32 m s f o r t h e cs5012a -7 v ersion only) must be all o wed for signal acquisition before hold is act i v ated. un- der microprocesso r -independent operation ( cs, rd l o w; a0 high) the cs5014 s and cs5016 s eoc output will not f all at the completion of the calibration c ycle, b ut e o t wi l l fall 15 clkin c ycles late r . initiating c alibration all modes of calibration can be controlled in h a rdw a r e or so f tw a r e . a c cur a c y c an th e r e by be insured at a n y time or temperature throughout op- erating life. after initial calibration at p o we r -up, the cs5012a/14/16 s cha r ge-redistri b ution design yields better temperature drift and more graceful aging than resisto r -based technologies, so calibra- ti o n is n ormally only required once, after p o w e r -up. the f irst mode of calibration, reset, results in a single full calibration c ycle. the second type of calibration, " b urst" cal, all o ws control of partial calibration c ycles. due to an unfo r e se e n c o n - didtion inside the part, asyn c h r onous termination of calib r ation may r esult in a sub-optimal r esult. burst cal should not be used. c r +5v rst cs5012a/14/16 figure 6. power-on reset circuit cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-21
the reset calibration always w orks perfectl y , and should be used instead of b urst mod e . the cs5012 s and cs5012a/14/16 s very l o w drift o v er temperature means that, under most circum- stances, calibration will only need to be p e r f o r med a t p o w e r - up, using r e set. the cs5012a/14/16 f e atur e a b a ckg r ound c a li- bration mode called "interle a v e." interle a v e appends a single calibration e xperiment to each co n v ersion c ycle and thus requires no dead time for calibration. the cs5012a/14/16 gathers data between co n v ersions and will adjust its transfer function once it completes the entire sequence of e xperiments (one calibration c y cle per 2,014 con- v ersions in the cs5012a and one calibration per 72,051 co n versions in the cs5012, cs5014 and cs5016). initiated by bringing both the intr l v input and cs l o w (or hard-wiring intr l v l o w), interle a v e e xtends the cs5012a/14/16 s e f fect i v e co n v ersion time by 20 clkin c ycles. other than reduced throughput, interle a v e is totally transpar- ent to the use r . interle a v e calibration should not be used intermittentl y . the f act t h at t h e cs 5 012a/14/16 o f fer s e v eral calibration modes is not to imply that the d e vices ne e d to b e r e c a lib r at e d oft e n. the d e vi c es a re v ery stable in the presence of la r ge temperature changes. t ests h a v e indicated that after using a single reset calibration at 25 c most d e vices e x- hibit very little change in o f fset or gain when exposed to temperatures from -55 to +125 c. the data indicated 30 ppm as the typical w orst case total change in o f fset or gain o v er this tem- perature range. di f ferential linearity remained v irt u ally u n c h a n ged. system err o r s o urces o utsi d e of the a/d co n v erte r , whether due to changes in temperature or to long-term aging, will generally dominate total system erro r . microprocessor interface the cs5012a/14/16 feature an intelligent micro- p r o cessor interface which o f fers detailed status information and all o ws soft w are control of the self-calibration functions. output data is a v ailable in either 8-bit or 16-bit formats for easy inter f ac- ing to industry-standard microprocessors. strobing both cs a n d r d l o w enables the cs5012a/14/16 s 3-state output b u f f e r s with eithe r output d a ta or st a tus in f o r mation d e p e nding on the status of a0. an address bit can be con- nected to a0 as sh o w n in figure 4b th e r e by memory mapping the status r e gister and output d a ta. co n v e rsion st a tus c a n b e poll e d in so f t w a re by reading the status r e gister ( cs and rd strobed l o w with a0 l o w), and masking status bits s0-s5 and s7 (by logically a n d ing th e status w ord with 01000000) to determine the v alue of s6. similarl y , the soft w are routine can determine calibration status using other status bits (see t a- b le 2) . ca r e must be taken not to r ead the status r e gister (a0 low) while hold is lo w , or a soft- wa r e r eset will r esult (s e e r e set a bov e ). alternat i v el y , the end-of-co n v ert ( e oc) output can be used to generate an interrupt or dr i v e a dma controller to dump the output directly into memory after each co n v ersion. the eoc pin falls as each co n v ersion c ycle is completed and data is v alid at the output. it returns high w ithin four clkin c ycl e s of th e f irst subsequ e nt d a ta r e ad ope r ation o r a ft e r th e st a rt o f a n e w co n v e r sion c y c l e . cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-22 ds14f 7
t o inter f ace with a 16-bit data b us, the bw input to th e cs5012a/14/16 should be held high a n d all data bits (12, 14 and 16 for the cs5012a, cs5014 a nd cs5016 r e sp e ct i v ely) r e a d in p a r a l- lel on pins d4-d15 (cs5012a), d2-d15 (cs5014), or d 0 - d15 ( cs5016). w ith a n 8-bit b us, the co n v erter s result must be read in two portions. in this instance, bw should be held l o w and the 8 msb s obtained on the f i rst read c ycle foll o wing a co n v ersion. the second read c ycle will yield the remaining lsb s (4, 6 or 8 for the cs5012a/14/16 respect i v ely) with 4, 2 or 0 trail- ing z e ros. both byt e s app e a r on pins d0-d7. the upper/l o wer bytes of the same data will continue to toggle on subsequent reads until the n e xt con- version f inish e s. st a tus bit s2 indi c at e s which byte will appear on the n e xt data read operation. the cs5012a/14/16 internally b u f fer their output data, so data can be read while the d e vices are tracking or co n v erting the n e xt sample. therefore, retri e ving the co n v erters digital output requires no reduction in adc throughput. enabling the 3- state outputs while the cs5012a/14/16 is co n v erting will not introduce co n v ersion errors. connecting cmos logic to the digital outputs is recommended. s uitable logic families include 4000b, 74hc, 74 a c, 74 a c t , and 74hc t . p i n s t a tus bit s t a tus de f in i t i on d0 s0 end of conversion f a l l s u p on c o m p l eti o n of a c o n v er s i o n, a n d r e t u r ns h i g h o n t h e f irs t s u bse q u e n t r e a d . d1 s1 rese r ved rese r v ed f or f ac t o r y use. d2 s2 l o w by t e/ high byte w h e n d a t a is t o be r e ad i n an 8 -b i t f o r m at (b w = 0 ), i n d i c a t e s wh i ch b y te w i ll a p p e a r a t t h e o u t p ut n e x t . d3 s3 end of tr a ck w h e n l o w , i n d i c a t e s t h e i n p u t h a s b e e n a c q u i re d t o t h e d e v i c e s s p e c i f i e d a c c u r a c y . d4 s4 rese r ved rese r v ed f or f ac t o r y use. d5 s5 t r a ck i ng h i g h w h e n t h e d e v i c e i s t r a c ki n g t h e i n p u t. d6 s6 conve r t ing hi g h wh e n t h e d e v i c e is c o n ve r t i ng t he h e l d i n p u t. d7 s7 cal i br a t i ng hi g h wh e n t h e d e v i c e is c a l i b r a t i n g . tabl e 2. status pin definitions d7 d 0 d5 d3 d2 d 1 d6 d 4 d1 2 d1 1 d10 d9 d 8 d1 5 d1 4 d13 x x x xx x x x s7 s6 s5 s4 s3 s2 s1 s0 8- or 16-bit data bus data (a0=1) status (a0=0) "x" denotes high impedance output x x x xx x xx 8-bit bus (bw=0) 16-bit bus (bw=1) b5 b 4 b11 b10 b7 b 6 b 8 b9 cs5012a cs5014 cs5016 b13 b11 b9 b7 b 6 b12 b10 b8 b5 b 4 b1 1 b10 b7 b 6 b 8 b9 b15 b13 b11 b9 b 8 b14 b12 b10 b3 b2 b1 b0 0 0 00 b5 b4 b3 b2 0 0 b1 b0 b7 b6 b5 b4 b1 b 0 b3 b2 b3 b2 b1 b0 0 0 00 x x x xx x xx b7 b 6 b13 b12 b9 b 8 b1 0 b11 b5 b4 b3 b2 0 0 b1 b0 x x x xx x xx b9 b 8 b15 b14 b1 1 b1 0 b1 2 b13 b7 b6 b5 b4 b1 b 0 b3 b2 cs5016 cs5014 cs5012a figur e 7. cs5012a/14/16 data f o r mat cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-23
microprocessor independent operation the cs5012a/14/16 c a n be op e r a ted in a stand- alone mode independent of intelligent control. in this mode, cs and rd are hard-wired l o w . this permanently enables the 3-state output b u f fers and all o ws transparent latch inputs (cal and intr l v) to be act i v e. a free-running condition is established when bw is tied high, cal is tied l o w , and hold is continually strobed l o w or tied to e o t. the cs5012a/14/16 s e oc output c an be used to e xternally latch the output data if de- sired. w ith cs and rd har d -wired l o w , eoc will strobe l o w for four clkin c ycles after each con- v ersion. data will be unstable up to 10 0 ns after eoc falls, so it should be latched on the rising edg e of e o c . se r ia l ou t put all success i v e-approximation a/d co n v erters de- r i v e their digital output serially starting with the msb. the cs5012a/14/16 present each bit to the s d a t a pin four clkin c ycles after it is der i v ed and can be latched using the serial clock output, sclk. just subsequ e nt to e a ch bit de c ision sclk will f all and return high once the bit infor- mation on s d a t a has stabilized. thus, the rising edg e o f th e scl k output should b e us e d to clock th e dat a f rom the cs5012a/14/16 (s e e figur e 9). analog circuit connections most popular success i ve-approximation a/d con- verters g e n erate d y namic l o a d s at t h eir a n al o g connections. the cs5012a/14/16 internally b u f f- er all analog inputs (ain, vre f , and a gnd) to ease the demands placed on e xternal circuitr y . h o w e v e r , accurate system operation still requires careful attention to details at the design stage re- ga r ding sou r c e imp e d a n c es a s w ell as g r ounding and d e coupling s c h e mes. reference considerations an application note titled " v olt a ge refe r ences for th e cs501x s e ries of a/ d co n v e rte r s " is a v ail- able for the cs5012a/14/16. in addition to worki n g t h r o u g h a reference circuit design e x am- p le, it o f fers s e v eral b uilt-and-tested reference circuits. during co n version, each capacito r o f th e c a l i - brated capacitor array is switched between vref and a gnd in a manner determined by the suc- cess i ve-approximation algorithm. the ch a r ging and discha r ging of the array results in a current load at the reference. the cs5012a/14/16 i n - clude an internal b u f fer ampli f ier to minimize the e xternal reference circuit s dr i v e requirement and preser v e the reference s int e grit y . when e v er the array is switched during co n v ersion, the b u f fer is u sed to p r e-cha r ge the array thereby providing t h e bulk of t h e necessary c h a r ge. t h e a p pro p riate array capacitors are then switched to the un b uf- fered vref pin to a v oid any errors due to o f fsets and/or noise in the b u f fe r . t h e e x ter n al reference circuitry n eed o nly pro- vide the residual cha r ge required to fully cha r ge th e arr a y a f t e r pre-cha r ging from th e b u f fe r . this creates an ac current load as the cs5012a/14/16 sequ e n c e through co n v ersions. the r e f e r e n c e cir- cuitry must h a v e a l o w enough output impedance to dr i v e the requisite current without changing its output v oltage signi f icantl y . as the analog input signal v aries, the switching sequence of the inter- n al capacit o r array c h a n ges. t h e c u rre n t load o n the e xternal reference circuitry thus v aries in re- sponse with the a n a log input. the r e f o r e, the e x ternal reference must not e xhibit signi f icant bw c a l r s t r e s e t a0 cs ho l d + 5 v s a m p l i n g c l o ck rd d4 d 1 5 d a ta o u t 12-bit eoc l a t c h i ng o u tput i n t r l v cs5 0 1 2 a c s 5 0 14 c s 5 0 16 figure 8. microprocessor-independent connections cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-24 ds14f 7
peaking in its output impedance characteristic at signal f r equ e n c ies o r thei r ha r monics. a la r ge capacitor connected between vref and a gnd can p r o vide su f f i c iently l o w output im- p e d a n c e a t th e high e nd o f th e f r equ e n c y s p ectrum, while almost all precision references e xhibit e xtremely l o w output impedance at dc. the magnitude of the current load on the e xternal reference circuitry will scale to the clkin fre- quen c y . at full speed, the reference must supply a maximum load current of 10 m a pea k -t o - p eak (1 m a typical). for the cs5012a an output im- p e d a n c e o f 15 w will therefore yield a maximum e r ro r o f 150 m v . w ith a 2.5 v r e f e r enc e a nd lsb size o f 600 m v, thi s w ould insur e bette r tha n 1/4 lsb accura c y . a 1 m f capacitor e xhibits an im- p e d a n c e o f l e ss than 15 w at fre q uencies g reater than 10 khz. similarl y , for the cs5014 with a 4.5v reference (27 5 m v/lsb), better than 1/4 lsb accura c y can be insured with an output imp e d a n c e of 4 w or less (maximum error of 40 m v). a 2 . 2 m f capacitor e xhibits an imped- ance of less than 4 w at frequencies greater than 5 khz. f o r t h e cs5016 with a 4.5v reference (69 m v/lsb ) , b e tte r th a n 1/4 lsb a c cur a c y c an be insured with an output impedance of less than 2 w (maximum error of 20 m v). a 20 m f capaci- tor e xhibits an impedance of less than 2 w at frequencies greater than 16 khz. a high-quality tantalum capacitor in parallel with a smaller ce- ramic capacitor is recommended. c l kin e o c status e o t ho l d s c l k s d a t a t d t d d e term i n ed lsb f i n e c h a r ge d e term i n ed m s b d e term i n ed m sb - 1 d e t e rmi n ed msb - 2 c o arse ch a r g e ls b +1 l s b msb msb - 1 ls b +2 2 4 6 8 10 1 2 6 4 6 2 60 8 0 / 0 76 7 8 7 4 7 2 7 0 6 8 6 6 cs5 0 16: 2 4 6 8 10 1 2 5 6 54 7 2 / 0 68 7 0 6 6 6 4 6 2 6 0 5 8 5 2 cs5 0 14: 2 4 6 8 10 1 2 4 8 4 6 44 6 4 / 0 60 6 2 5 8 5 6 5 4 5 2 5 0 cs 50 12a: figure 9. serial output timing notes : 1 . synchronous (loopback) mod e is illustrated . after eoc falls th e co n verte r goe s into coarse cha r ge mod e for 6 clkin c y c les, then to f ine cha r ge mod e for 9 c y c les, then e o t falls. i n lo o p b ack m o de, e o t tri p s hold which c aptu r es th e a n a log s a mple . co n v e r sion b e gins on the n e xt rising edg e of c l kin . i f ope r at e d asyn c h r o- n o usl y , e o t will remain l o w unti l after hold is taken l o w . when ho l d o c c u r s t h e a n al o g sa m ple is c a pt u r e d immediatel y , b ut co n version may no t begin unti l four clkin cycles late r . e o t will return high when c o n v ersion b e gins. 2 . t iming d ela y t d (relat i ve to clkin ) can v ary between 13 5 ns to 23 5 ns o ver the military temperatur e range a n d over 10 % supply v ariation 3. eoc returns high in 4 clkin cycles if a0 = 1 and cs = rd = 0 (micr o process o r i n depen d e n t m o de); within 4 clkin cycles after a data rea d (microprocessor mode); or 4 clki n c ycles after hold = 0 is r e cogniz e d on a r ising e dge o f clk i n/4. cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-25
pea k ing in t h e refere n ce s o ut p ut im p e d a n ce can occur because of capacit i v e loading at its output. any pea k ing t h at mig h t occ u r can be red u ced b y placing a small resistor in series with the capaci- tors (figure 10). the equation in figure 10 can be used to help calculate the optimum v alue of r for a particular reference. the term "f peak " is the freq u e n c y o f t h e peak in t h e o u tp u t im p e d a n ce o f t h e reference bef o re t h e resistor is a d ded. the cs5012a/14/16 can operate with a wide ra n ge of reference v oltages, b ut signal-to-noise p erformance is maximized by using as wide a signal r a nge as possibl e . th e r e commend e d r e f e r - ence v oltage is between 2.5 and 4.5 v for the cs5012a a nd 4.5 v for the cs5014/16. the cs5012a/14/16 can actually accept reference v oltages up to the posit i v e analog suppl y . h o w- e ve r , the b u f f er s o f fset may increase as the refere n ce v oltage approache s v a + t h e r e b y i n - creasing e xternal dr i v e requirements at vre f . a 4.5v reference is the maximum reference v oltage recommended. this all o ws 0.5v headroom for t h e inter n al reference b u f fe r . also, the b u f fer en- lists the aid of an e xternal 0.1 m f c eramic capacitor which must be tied between its output, refbu f , and the n e gat i ve analog suppl y , v a-. f or more information on references, consult the applica- tion note: v oltage references for the cs501x se- ries o f a/d c o n verters. for an e xample of usi n g the cs5012a/14/16 with a 5 v olt reference, see the application note: a collection of application hints for the cs501x series of a/d co n verters. analog input connection the analog input terminal functions similarly to t h e v ref i n put after each co n version when switching into the track mode. during the f i rst six clkin c ycles in the track mode, the b u f fered versi o n of t h e a n al o g in p ut is u sed for pre-c h a r g- ing the capacitor arra y . an additional period is required for f i ne-cha r ging directly from ain to v r e f r e f b uf v a - 0 . 1 m f -5v r 29 28 30 r e f v c1 1.0 m f 0. 0 1 m f c2 +v ee cs5 0 1 2 a c s 5 0 1 4 c s 5 0 1 6 1 r= 2 p (c 1 + c 2 ) f peak figure 10 . reference connections i n ter n a l c h a r g e er r o r (l sb 's) fine-charge pre-charge acquisition time (us) 0.5 1.0 1.5 2.0 2.5 (delay from eoc) +12.5 0 -12.5 -25.0 +50 0 -50 -100 +200 0 -200 -400 cs5012 a cs501 4 cs5016 figure 11. internal acquisition time cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-26 ds14f 7
obtain the speci f ied accura c y . figure 11 illustrates this ope r ation. du r ing pr e - c h a r ge th e cha r g e on the capacitor array f i rst settles to the b u f fered v er- sion of the analog input. this v oltage is o f fset from the actual input v oltage. during f i ne-cha r ge, the cha r ge then settles to the accurate un b u f fered v e r s i o n. the acquisition time of the cs5012a/14/16 de- p e nds on th e clk i n f r equ e n c y . this is du e to a f i x ed p r e - cha r g e p e riod. f or instanc e , op e r a ting the cs5012a -12, cs5014 -14 or cs5016 -16 v ersion with an e xternal 4 mhz clkin results in a 3.75 m s acquisition time: 1. 5 m s for pre-c h a r gi n g (6 clock c y cles) and 2 . 25 m s f o r f ine-cha r ging. fine-cha r ge settling is speci f ied as a maximum of 2.25 m s for an a n al o g s o urce impedance o f less th a n 20 0 w . (for the cs5012a -7 version it is sp e ci f ied a s 1.32 m s.) in addition, the comparator re q uires a so u rce im p e d a n ce of less t h an 4 0 0 w around 2 mhz for stabilit y , which is met by prac- tically all bipolar op amps. l a r ge dc source im p e d a n ces can b e acc o mmo d ated by ad d ing ca- p a cit a n c e f rom a i n to g r ound ( typic a lly 200 pf) to decrease s o urce im p e d a n ce at h igh freq u e n cies. h o w e v e r , high dc source resistances will increase the input s rc time constant and e xtend the nec- essary acquisition time. for more information on input applications, consult th e appli c ation not e : input bu f fer ampli f iers for the cs501x f amily of a/d co n v ert e r s . during the f irst six clock c ycles foll o wing a con- version (pre-cha r g e) in unipolar mode, the cs5012a is c a p a bl e of sl e wing at 20 v / m s and the cs5014/16 can sl e w at 5v/ m s. in bipolar mode, only half the capacitor array is connected to the analog input so the cs5012a can sl e w at 40 v / m s, and th e cs5014/16 c a n sl e w at 10v/ m s. after the f i rst six clkin c ycles, the cs5012a will sl e w at 1.25 v / m s in unipola r mod e a nd 3.0 v / m s in bipolar mode, and the cs5014/16 will sl e w at 0.25v / m s in unipola r mode a nd 0.5 v / m s in bipolar mode. acqu i s i tion of f ast sl e wing signals (step fun c - tions) c an b e h a stened if th e st e p o c curs during or immediately foll o wing the co n v ersion c ycle. f or instance, channel selection in multipl e x ed appli- cations should occur while the cs5012a/14/16 is co n v erting (see figure 12). multipl e x er settling is t h ere b y rem o ved from the o verall throughput equation, and the cs5012a/14/16 can co n v ert at full speed. c o n v e r t c h a n nel n + 1 conv e r t cha n nel n a d d r e s s n a d d r ess n + 1 a dd r ess n + 2 a dd r ess n + 3 e o c o u t p ut hold i n p u t m u x a d d r ess m u x s e t t l i ng t o cha n ne l n + 2 a n a l o g i n p u t m u x s e ttl i ng t o cha n ne l n + 1 c s 501 2 a/ 1 4/16 c s 501 2 a/ 1 4/16 c s 501 2 a/ 1 4/16 figure 12 . pipelined mux input channels cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-27
analog input range/coding format the reference v oltage directly de f ines the input voltage range in both the unipolar and bipolar co n f i g urati o ns. in the unipolar con f iguration (bp/ u p l o w), the f i rst code transition occurs 0.5 lsb ab o v e a gnd, a nd the f inal cod e t r ansi- tion occurs 1.5 lsb s bel o w vre f . coding is in straight binary format. in the bipolar con f igura- tion (bp/ up high), the f i rst code transition occurs 0.5 lsb ab o v e -vref and the last transition oc- curs 1.5 lsb s b e l o w + v re f . coding is in an o f fset-binary format. posit i ve full s c al e g i v es a digital output of all ones, and n e gat i v e full scale g i v es a digital output of all zeros. the bp/ up mode pin may be switched after cali- bration without h a ving to rec a lib r at e the co n v erte r . h o w e v e r , the bp/ up mode should be changed during the pr e vious co n v e r sion c y c le, that is, between hold f alling and eoc f alling. if bp/ u p is c h a n ged at any other time, one d ummy c o n version c ycle must be all o wed for proper acquisition of the input. grounding and power supply decoupling the cs5012 a /14/16 us e th e analog g r ound c on- nection, a gnd, only as a reference v oltage. no dc p o wer currents fl o w through the a gnd con- nection, and it is complet e ly ind e p e ndent of dgnd. h o w e v e r , a n y noise riding on th e a gnd input relat i v e to the system s analog ground will i n d u ce c o n version err o rs. t h erefore, b o th t h e a n a- log input and reference v oltage should be referred to the a gnd pin, which should be used as the entire system s analog ground reference point. the digital and analog supplies to the cs5012a/14/16 are pinned out sepa r at e ly to minimize coupling between the analog and digital sections of the chip. all four supplies should be decoupled to their respect i ve grounds using 0. 1 m f ceramic capacitors. if signi f icant l o w-fre- quency noise is present on the supplies, 1 m f tantalum capacitors are recommended in parallel with the 0.1 m f capacitors. the positive digital power supply of the c s 5 0 1 2 a/ 1 4/ 1 6 must n e ver e xceed the positive analog supply by mo r e than a diode d r op or the d e vice could e xperience permanent damag e . if the t w o supplies are der i v e d f rom sepa r ate sources, care must be taken that the analog sup- p ly comes up f irst at p o we r -up. the system connection diagram in figure 36 sh o ws a decou- pling scheme which all o ws the cs5012a/14/16 to b e p o w e r e d f r om a single set o f 5v rails. as with a n y high-precision a/d co n v erte r , the cs5012a/14/16 require careful attention to grounding and layout arrangements. h o w e ve r , no unique l a yout issues must b e add r ess e d to p r op- erly apply the d e vice. the cdb5012/14/16 e v aluation boa r d is a v a ilable f o r the cs5012a/14/16, which a v oids the need to d e - sign, b uild, and de b ug a high-precision pc board to initially characterize the part. the board comes with a socketed cs5012a/14/16, and can be quickly recon f igured to simulate a n y combination of sampling, calibration, clkin, and analog in- put range conditions. cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-28 ds14f 7
power supply rejection the cs5012a/14/16 s p o wer supply r e je c tion p e r f o r manc e is enh a n c ed by the on- c hip s e lf - c a li- bration and an "auto-zero" proce s s. drift s in p o wer supply v oltages at frequencies less than the calibration rate h a v e n e gligible e f fect on the cs5012a/14/16 s a c cur a c y . this is b e c a us e the cs5012a/14/16 adjust thei r o f f set to within a small fraction of an l s b during calibration. abo v e the calibration frequen c y the e xcellent p o wer supply rejection of the internal ampli f iers is augmented by an auto-zero pro c ess. a n y o f fsets are stored on the capacitor array and are e f fect i v ely subtracted once co n v ersion is initiated. figure 13 sh o ws p o wer supply rejection of the cs5012a/14/16 in the bipolar mode with the analog input ground e d an d a 300 mvp - p ripple applied to each suppl y . p o wer supply r e je c tion impr o v e s by 6 db in the unipolar mode. the plot in figure 13 sh o ws w orst-case rejection for all combinations of co n v ersion rates and input conditions in the bipolar mode. cs5012a/14/16 performance differential nonlinearity one source of nonlinearity in a/d co n v erters is b it weig h t err o rs. t h ese err o rs arise from t h e d e- viation of bits from their ideal binary-weighted rati o s, a n d lead to n o ni d eal widt h s for each c o de. if dnl errors are la r ge, and code widths shrink to zero, it is possible for one or more codes to be entirely missing. the cs5012a/14/16 calibrate all bits in the capacitor array to a small fraction of an lsb resulting in nearly ideal dnl. histo- gram plots of typical dnl of the cs5012a/14/16 can be seen in figures 14, 16, 17. figure 15 il- lustrates the dnl of the cs5012 for comparison with the cs5012a (figu r e 14). a histogram test is a statistical method of der i v- ing an a/d co n v erter s di f ferential nonlinearit y . a ramp is input to the a/d and a la r ge number of samples are ta k en to insure a high con f idence l e v el in the test s result. the number of occur- re n ces f o r each co d e is m o nit o red a n d store d . a perfect a/d co n v erte r would h a v e a ll cod e s of equal size and therefore equal numbers of occur- rences. in the histogram test a code with the a verage number of occurrences will be consid- ered ideal (dnl = 0). a code with more or less occurrences than a v erage will appear as a dnl of greater or less than zero lsb. a missing code has zero occurrences, and will appear as a dnl o f - 1 lsb. integral nonlinearity int e gral nonlinearity (inl; also termed relat i v e accura c y or just nonlinearity) is de f ined as the d e viation of the transfer function from an ideal straight line. b o ws in the transfer cur v e generate harmonic distortion. the w orst-case condition of bit-weight errors (dnl) has traditionally also de- f ined the point of maximum inl. bit-weight errors h a v e a drastic e f fect on a con- v e r te r s a c pe r form a n c e. th e y c a n b e a n a ly z ed a s step functions superimposed on the input signal. power supply ripple frequency 1 khz 10 khz 100 khz 1 mhz p o w e r s u p p ly r e je c t io n ( d b ) 90 80 70 60 50 40 30 20 figure 13. powe r supply rejection cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-29
0 4,095 codes 2,048 dnl (lsb) +1 0 -1 +1/2 -1/2 f igu r e 14. cs5012 a di f f e r e ntial nonlineari t y plot 0 4,095 codes 2,048 dnl (lsb) +1 0 -1 +1/2 -1/2 f igu r e 15. cs5012 di f f e r e ntial nonlineari t y plot 0 16,383 codes 8,192 dnl (lsb) +1 0 -1 +1/2 -1/2 f igu r e 16. cs5014 di f f e r e ntial nonlineari t y plot 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 f igu r e 17. cs5016 di f f e r e ntial nonlineari t y plot cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-30 ds14f 7
si n ce bits (and their errors) switch in and out throughout the transfer cur v e, their e f fect is sig- nal dependent. that is, ha r monic a nd intermodulation distortion, as well as noise, can v ary with di f ferent input conditions. designing a system around characterization data is risky since transfer cur v es can di f fer drastically unit-to-unit and lot-to-lot. the cs5012a/14/16 a c hi e v e s r epe a table signal- to-noise and harmonic distortion per f o r mance using an on-chip self-calibration scheme. the cs5012a calibrates its bit weight error s to a small fraction of an lsb at 12-bits yielding peak distortion bel o w th e noise f loor ( se e figur e 19). the cs5014 calibrates its bit weights to within 1/16 lsb at 14-bits ( 0.0004% fs) yielding peak distortion as l o w as - 105 db (s e e fi g - ure 22). the cs5016 calibrates its bit weights to within 1/4 lsb a t 16-bits ( 0.0004% fs) yield- ing peak distortion as l o w as -105 db ( see figure 24). unlike traditional adc s, the linear- ity of the cs5012a/14/16 are not limited by bit-weight errors; their performance is therefore extre m ely repeatable and independent of input signal conditions. quantization noise the error due to quantization of the analog input ultimately dictates the accura c y of a n y a/d con- verte r . the continuous a n a log input must be r e p r es e nt e d by on e of a f inite numb e r o f digit a l co d es, so t h e best accura c y to which an a n al o g input can be kn o wn from its digit a l cod e is 1/2 lsb. under circumstan c es c ommonly en- countered in signal processing applications, this quantization error can be tr e at e d a s a r andom v ariable. the magnitude of the error is limited to 1/2 lsb, b ut a n y v alue within this range has eq u al p r o bability of occurrence. such a pro b - ability distri b ution leads to an error "signal" with an rms v a lu e o f 1 lsb/ ? 1 2 . using an rms sig n al v alue of fs/ ? 8 (amplitude = fs/2), this relates to id e al 12, 14 a nd 16 - bit signal - to - noise r atios of 74, 86 an d 98 d b respect i vel y . equally important is the spectral content of this error signal. it can be sh o wn to be approximately white, with its ene r gy spread uniformly o v er the b a nd f r om dc to one - h a lf the s a mpling r at e . ad- v antage of this characteristic can be made by judicious use of f iltering. if the signal is ban- dlimited, much of the quantization error can be f iltered out, and impr o v ed sy s t em performance can be attained. fft tests and windowing in t h e factor y , t h e cs5 0 1 2 a/ 1 4/ 1 6 are tested us- ing f ast fourier t ransform (fft) techniques to analyze the co n v erter s dynamic performance. a pur e sin e w a v e is appli e d to th e cs5012a/14/16, and a "time record" of 1024 samples is captured and p r o c ess e d. th e fft a lgorithm a n a ly z es the spectral content of the digital w a v eform and dis- tri b ut e s its ene r gy among 512 " f r e quen c y bins." assuming an ideal sin e w a v e, distri b ution of en- e r gy in bins outside of the fundamental and dc can only be due to quantization e f fects and errors in the cs5012a/14/16. if sampling is not synchronized to the input sine- w a v e, it is highly unlikely that the time record will contain an int e ger number of periods of the input signal. h o w e v e r , the fft assumes that the signal is periodic, and will calculate the spectrum of a signal that appears to h a v e la r ge discontinui- ties, thereby yielding a s e v erely distorted spectrum. t o a v oid this problem, the time record is multiplied by a wind o w function prior to per- forming the ff t . the wind o w function smoothly forces the endpoints of the time record to zero, thereby rem o ving the discontinuities. the e f fect of the wind o w in the frequen c y-domain is to con- v olute the spectrum of the wind o w with that of the actual input. figur e 18 sh o ws an fft c omput e d f r om an ide a l 12-bit sin e w a v e. the quality of the wind o w used for harmonic analysis is typically judged by its h ig h est si d e-lo b e l e vel. t he blackman-harris wind o w used for testing the cs5014 and cs5016 has a maximum side-lobe l e v el of -92 db. fig- cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-31
u r es 21 a nd 23 sh o w fft plots c omput e d f rom an ideal 14 and 16-bit sin e w a v e multiplied by a bla c km a n - h a r r is wind o w . arti f a c ts o f wind o w- ing are discarded from the signal-to-noise calculation using the assumption that quantization noise is white. all fft plots in this data sheet were der i v ed by a v eraging the fft results from ten 1024 point time records. this f ilters the spec- tral v ariability that can arise from capturing f inite time records without disturbing the total ene r gy outside the fundamental. all harmonics which e x- ist ab o v e the noise floor and the -92 db side-lobes from the blackman-harris wind o w are t h erefore clearly v isible in t h e p lots. f o r m o re in- formation on fft s and wind o wing refer to: f .j. harris, "on th e use o f wind o w s for h a rmonic dc 50.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 sampling rate: 100khz full scale: 9vp-p s/n+d: 72.9db input frequency (khz) 12.0 signal amplitude relative to full scale (db) figure 2 0 . fft pl o t of cs 5 0 1 2 a with 12 k h z full-scale input dc -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 input frequency signal amplitude relative to full scale (db) s/n+d: 73.9 db f / 2 s figure 1 8 . pl o t of ideal 1 2 -bit adc dc 50.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 input frequency (khz) 1.0 signal amplitude relative to full scale (db) sampling rate: 100khz full scale: 9vp-p s/n+d: 73.6db f igu r e 19 . plot o f cs5012a with 1 kh z full scale input signal amplitude relative to full scale dc 0db -20db -40db -60db -80db -100db -120db 28 khz 1 khz sampling rate: 56 khz full scale: 9v p-p s/(n+d): 85.3 db input frequency f igu r e 22. cs5014 f ft plot with 1 kh z full scale input signal amplitude relative to full scale dc input frequency s/(n+d): 86.1 db 0db -20db -40db -60db -80db -100db -120db f /2 s f igu r e 21. plot o f id e al 14-bi t adc cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-32 ds14f 7
analysis with the discrete f ourier t ransform", proc. ieee, v ol. 66, no. 1, jan 1978, pp.51-83. this is a v ailable on request from crystal semi- condu c to r . figur e s 19, 22, and 24 sh o w th e pe r form a n c e of the cs5012a/14/16 with 1khz full scale inputs. figure 20 sh o ws cs5012a performance with 12khz full scale inputs. notice that the perform- ance cs5 0 1 2 a/ 1 4/ 1 6 cl o sely a p proac h es t h at o f the corresponding ideal adc. cs5012a high frequency performance the cs5012a performs very well over a wide range of input frequencies as sh o wn in figure 25. the f igu r e d e pi c ts the cs5012a - kp7 t e sted un- der four di f ferent conditions. the conditions include tests with the v oltage reference set at 4.5 and at 2.5 v olts with input signals at 0.5 db d o wn from full scale and 6.0 db d o wn from full scale. the sample rate is at 100 khz for all cases. the p lots i n dicate that the part performs very well e ven with input frequencies ab o ve the nyquist rate. best performa n ce at t h e hi g her fre q uencies is achi e v ed with a 2.5 v olt reference. 0 20 40 60 80 100 120 140 160 180 200 55 60 65 70 75 signal to noise + distortion input frequency (khz) / 2 f s f s cs5012a-kp7 f s =100 khz 2 1 3 4 4.5 2.5 4.5 2.5 fs-0.5db fs-0.5db fs-6.0db fs-6.0db 1. 2. 3. 4. vref signal (db) figure 25 . cs5012a high frequency input performance signal amplitude relative to full scale dc input frequency s/(n+d): 97.5 db 0db -20db -40db -60db -80db -100db -120db f /2 s figure 2 3 . pl o t of ideal 1 6 -bit adc signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 25 khz sampling rate: 50 khz full scale: 9v p-p s/(n+d): 92.4 db 1 khz f igu r e 24. cs5016 f ft plot with 1 kh z full scale input cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-33
signal to noise + distortion vs signal level as illustrated in figures 26 - 29, the cs5014/16 s on-chip self-calibration pr o vides v ery accurate bit w e ights which yi e ld no d e g r adation in quantiz a - tion noise with l o w-l e v el input signals. in fact, quantization noise remains bel o w the noise floor in the cs5016, which dictates the co n v erter s sig- nal-to-noise performance. cs5016 noise considerations all analog circuitry in the cs5016 is wideband in o r d er to achi e ve f ast co n versions and high th r oughput. w id e b a nd nois e in the cs5016 int e - g r at e s to 35 m v rms in unipolar mode (70 m v rms in bipolar mode). this is approximately 1/2 lsb rms with a 4.5v reference in both modes. figure 30 sh o w s a histogr a m plot o f output cod e oc c u r - rences obtained from 5000 samples ta k en from a cs5016 in the bipolar mode. h e xadecimal code 80cd was arbitrarily selected and the analog in- put w as set close to code cente r . w ith a noiseless co n v e r te r , cod e 80cd w ould a l w a ys a ppe a r . the histogram plot of the cs5016 has a "bell" shape with all codes other than 80cd due to internal noise. in a sampled data system all information about the analog input applied to the sample/hold appears in the baseband from dc to one-half the sampling rate. this includes high-frequen c y components which alias into the baseband. l o w-pass (anti-alias) f ilters analog input amplitude -100 d b -80 d b -60 d b -40 d b -20 db 0 db 100 db 80 db 60 db 40 db 20 db 0 db s(n+d) 1 khz 12 khz 24 khz input frequencies figure 26. cs5014 s/(n+d) vs. input amplitude (9vp-p full-scale input) analog input amplitude -100 d b -80 d b -60 d b -40 d b -20 db 0 db 100 db 80 db 60 db 40 db 20 db 0 db s(n+d) 1 khz 12 khz 24 khz input frequency figure 28. cs5016 s/(n+d) vs. input amplitude (9vp-p full-scale input) signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 28 khz 1 khz sampling rate: 56 khz full scale: 9v p-p s/(n+d): 24.1 db f igu r e 27. cs5014 f ft plot with 1 kh z -60 db input signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 25 khz sampling rate: 50 khz full scale: 9v p-p s/(n+d): 9.6 db 1 khz f igu r e 29. cs5016 f ft plot with 1 kh z -80 db input cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-34 ds14f 7
are t h erefore used to remove fre q uen c y com p o- nents in the input signal which are ab o v e one-half the sample rate. h o w e v e r , all wideband noise in- troduced by the cs5016 still alias e s into the baseband. this "white" nois e is e v enly spr e ad from dc to one-half the sampling rate and inte- g r at e s to 35 m v rms in unipolar mode. noise can be reduced by sampling at higher than the desired w ord rate and a veraging multiple samples for each word. o v ersampling spreads the cs 5 0 1 6 s noise o v er a wider band (for l o wer noise density), and a v eraging applies a l o w-pass response which f ilters noise ab o v e the desired signal bandwidth. in general, the cs5016 s noise performance can be maximized in a n y application b y always sampling at the maximum speci f ied rate of 50 khz (for l o west noise density) and digitally f iltering to the desired signal bandwidth. cs5014 and cs5016 sampling distortion the ultimate limitation on the cs5014/16 s linearity ( a nd distortion ) a r ises f rom nonide a l sampling of the analog input v oltage. the cali- b r at e d c a p a citor a r r a y us e d during co n v e r sions is also used to track and hold the analog input sig- n a l. th e co n v e r sion is not p e r f o r med on the analog input v oltage per se, b ut is actually per- formed on the cha r ge trapped on the capacitor ar- ray at the moment the hold command is g i v en. the cha r ge on the array is ideally related to the analog input v o lt a g e by q in = -v in x c tot as sh o wn in figure 2. a n y d e viation from this ideal relationship will result in co n v ersion errors e v en if th e c o n v e rsion p r o c ess p r o c e e ds fl a w lessl y . at dc, t h e da c capacit o r array s voltage coe f f i- cie n t dictates the c o n verter s linearit y . this v ariation in capacitance with respect to applied signal v oltage yi e lds a nonline a r r e lationship b e - tw e en cha r g e q in and the analog input v oltage v in and pla c es a b o w o r w a v e in th e tr a ns f er function. this is the dominant source of distor- tion at l o w input frequencies (figures 22 and 24). the ideal relationship between q in and v in can also be distort e d at high signal f r equ e n c ies due to nonlinearities in the internal mos switches. dy- namic signals cause ac current to fl o w through the switches connecting the capacitor array to the analog input pin in the track mode. nonlinear on- resistance in the switches causes a nonlinear v oltage drop. this e f fect worsens with increased signal frequen c y as sh o wn in figures 26 and 28 since the magnitude of the steady state current in- creases. first noticeable at 1 khz, this distortion assumes a linear relationship with input fr e - quen c y . w ith signals 20 db o r mo r e bel o w full-scale, it no longer dominates the co n v erter s overall s/(n+d) performance (figures 31-34). this distortion is strictly an ac sampling ph e - nomenon. if signi f icant ene r gy e xists at high frequencies, the e f fect can be eliminated using an e xternal track-and-hold ampli f ier to all o w the ar- ray s cha r ge current to deca y , thereby eliminating a n y v oltage drop across the switches. since the cs5014/16 has a second sampling function on- chip, the e xternal track-and-hold can return to the track mode once the co n v erter s h o l d input falls. it need only acquire the analog input by the time the entire co n v ersion c ycle f i nishes. code (hexadecimal) counts: 0 11 911 3470 599 9 0 80cb 80cc 80cd 80cf 80d 0 80c e 80ca 1000 2000 3000 4000 5000 count noiseless cs5016 converter figure 3 0 . histo g r a m plot o f 5 0 00 c o nversi o n inputs from the cs5016 cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-35
clock feedthrough in the cs5014 and cs5016 maintaining the int e grity of analog signals in the presence of digital switching noise is a di f f i cult problem. the cs5014/16 can be synchronized to t h e d igital system using the clkin input to a v oid co n v e r sion e r rors du e to a synchronous in- terference. h o w e v e r , digital interference will still a f fect sampling purity due to coupling between the cs5014/16 s analog input and master clock. the e f f e c t of clock f e e dthrough d e p e nds on the sampling conditions. if the sampling signal at the hold input is synchronized to the master clock, clock feedthrough will appear as a dc o f fset at the cs5014/16 s output. the o f fset could theoreti- cally reach the peak coupling magnitude (figure 35), b ut the probability of this occurring is small since the peaks are spi k es of short dura- tion. if sampling is performed asynchronously with the master clock, clock feedthrough will appear as an ac error at the cs5014/16 s output. w ith a f i x ed analog input source impedance 200 25 50 50 50 4mhz 2mhz master clock clock feedthrough int/ext freq internal external external external external 2mhz 4mhz 4mhz rms peak-to-peak 15uv 25uv 40uv 25uv 80uv 70uv 110uv 150uv 110uv 325uv f igu r e 3 5 . e x ampl e s o f m e asu r ed clo c k f e e dth r ou g h signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 28 khz sampling rate: 56 khz full scale: 9v p-p s/(n+d): 81.5 db 12 khz f igu r e 31. cs5014 f ft plot with 12 k h z full scale input signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 25 khz sampling rate: 50 khz full scale: 9v p-p s/(n+d): 84.3 db 12 khz f igu r e 33. cs5016 f ft plot with 12 k h z full scale input signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 25 khz sampling rate: 50 khz full scale: 9v p-p s/(n+d): 71.9 db 12 khz f igu r e 34. cs5016 f ft plot with 12 k h z -20 db input signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 28 khz sampling rate: 56 khz full scale: 9v p-p s/(n+d): 64.6 db 12 khz f igu r e 32. cs5014 f ft plot with 12 k h z -20 db input cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-36 ds14f 7
sampling rate, a tone will appear as the clock fre- quen c y aliases into the baseband. the tone frequen c y can b e c a lculat e d using th e equ a tion bel o w and could be select i v ely f iltered in soft- ware using dsp techniques. f tone = (n f s - f clk ) wher e n = f clk /f s rounded t o the neares t integer the magnitude of clock feedthrough depends on the master clock conditions and the source im- p e d a n ce a p plied to the a n alog input. when operating with the cs5014/16 s internally gener- ated cl o c k , t h e c l kin i n p u t is gro u n d ed a n d t h e dominant source of coupling is through the de- vi c e s subst r at e . a s sh o w n in figur e 35, a typic a l cs5014/16 operating with their internal oscillator a t 2 mhz an d 50 w of analog input source im- pedance will e xhibit only 1 5 m v r m s of clock feedthrough. h o w e v e r , if a 2 mhz e xternal clock is applied to clkin under the same conditions, feedthrough increases to 25 m v rms. feedthrough als o increase s with cloc k frequen c y ; a 4 mhz clock yields 40 m v rms. clock feedthrough can be reduced by limiting the source impedance applied at the analog input. as sh o wn in figur e 35, r edu c ing sour c e impedance f r om 50 w to 25 w yields a 15 m v rms reduction in feedthrough. therefore, when op e r a ting the cs5014/16 with high - f r equ e n c y e xt e rnal m a ster clocks, it is important to minimize source imped- ance applied to the cs5014/16 s input. also, the o v e r a ll e f f e ct o f c lo c k f e edth r ough c an be minimized by maximizing the input range and lsb size. the reference v oltage applied to vref can be maximized, and the cs5014/16 can be op- erated in bipolar mode which inherently doubles the lsb size o v er the unipolar mode. differences between the cs5012a and the cs5012 the di f f erences between th e cs5012a a nd the cs5012 a r e t a b ulat e d in t a bl e 3. t h e cs5012 is a short- c ycled version of the cs5016 a/d con- verter and includes the same 18-bit calibration circuitr y . this calibration circuitry sets the cali- bration resolution of the cs5012 at 1/64th of an l s b a n d ac h i e ves t he near perfect di f fere n tial linearity performance illustrated by the cs5012 dnl plot in figure 15. the cs5012a calibration circuitry w as modi f i ed to pr o vide calibration to 15-bit resolution therefore achi e ving c alibr a tion to 1/8 of an lsb. this reduction in calibration resolution for the cs5012a reduces the time re- quired to calibrate the d e vice (see t able 3) and reduces the size of the total array capacit a n c e. the red u ced array capacitance im p roves t h e hi g h f r equ e n c y p e r f o r manc e by all o w ing highe r sl e w rate in the input circuitr y . t able 3 documents some other impr o v ements in- cluded in the cs5012a. the b urst mode calibration w as made functional, although it should not b e us e d. the d e vi c e w as a lso modi f ied so the eoc signal goes l o w at the end of a reset calibration in either microprocessor or microproc- esso r -independent mode. the cs5012 a w a s modi f i ed to maintain a throughput rate of 64 clkin c ycles in loopback mode for all frequen- cies of clkin. schematic & layout review service confir m optimum schemati c & layout befor e buildin g y ou r board. fo r ou r fre e revie w service cal l application s engineering. call : (512 ) 445-7222 cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-37
calibration resolution calibration time reset: interleave: burst: end of calibration indicator throughput rate in loopback mode input capacitance in fine-charge mode cs5012 18 bits. results in dnl calibration to 1/64 lsb at 12 bits. 1,441,020 clkin cycles 72,051 conversions not functional eoc falls at the completion of a reset calibration cycle in microprocessor mode only. in microprocessor-independent mode cycles after completion of a reset calibration. the device acquires and converts in 64 clkin cycles for clkin=4mhz, but will require 68 clkin cycles at 100khz through- put. this is due to excess delay on 275pf typical, unipolar mode cs5012a 15 bits. results in dnl calibration to 1/8 lsb at 12 bits. 58,280 clkin cycles 2,014 conversions fully functional eoc falls in either microprocessor or microprocessor-independent mode at the completion of a reset calibration cycle. the device acquires and converts a sample in 64 clkin cycles for all clkin frequencies when in loopback. 103pf typical, unipolar mode eot must be used. eot. slew rate unipolar coarse charge fine charge bipolar coarse charge fine charge falls 15 clki n eot 20v/us 1.5v/us 40v/us 3.0v/us 5v/us 0.25v/us 10v/us 0.5v/us 72pf typical, bipolar mode 165pf typical, bipolar mode tabl e 3. diff e r e nc e s betwe e n th e cs5012a and cs5012 cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-38 ds14f 7
figure 3 6 . cs5 0 1 2 a/1 4 /16 s y stem c o nnecti o n di a gram 26 28 29 30 25 27 11 10 36 v r e f ain r e f b uf v a - a g n d v a + v d + d g nd v d - +5v - 5 v 10 w 10 w v o l t a ge r e f e r e n ce r e s e t generator d a ta p r o c e s s o r s e r i al d a t a i n t e r f a c e ( op t i on a l ) c l o c k s o u r ce ( o p t i o n a l ) cont r ol l o gic m o de s e l e ct * a n a l og s u p p ly s o u r ce s i gnal a n a l og s u p p ly a n a l og tst bw r es e t a0 c a l d 0 - d 1 5 sc l k s d a t a c l kin 24 33 20 40 39 8 or 16 38 37 1 35 34 21 22 23 32 31 0. 1 m f 0.0 1 m f 0.1 m f 0 . 1 m f m a y be m i c ro p r o c e s s o r or d i s c rete l ogi c . 0. 1 m f in t r l v e o c e o t hold bp/ u p rd cs 0.1 m f cs5 0 1 2 a or v r ef vr e f 0 1 0 m f s i g n a l c o n d i t i o n i n g 1 0 00 pf 20 0 w c s 5 0 1 4 c s 5 0 1 6 un u s ed l ogic i npu t s s h o u l d on l y b e c on n ec t e d t o vd + o r dgnd. * b w a n d bp / u p s h ou l d alwa y s b e t e rmi n ated to v d + o r dgnd, f o r b e st dyna m ic s / ( n + d ) p e r f o rm a n c e . o r d r i v en by a lo g ic g a te. functio n rs t a 0 cal hold and start convert initiate burst calibration stop burst cal and begin track initiate interleave calibration terminate interleave cal read output data read status register high impedance data bus high impedance data bus reset reset 0 0 0 0 0 0 0 x x 1 x * * * * * 1 0 * * x 0 x x x x x 0 0 x 1 x x x x x 0 1 x x x x x x x 1 0 x x x x x x x x x 0 0 0 0 0 0 1 x x 0 x 1 x x x 1 x x x 0 hold cs intrlv rd table 4 . cs5012a/14/16 truth table * t h e stat u s o f a0 is n ot critical to th e o p eration s p ecifie d . h o w e ve r , a 0 sh o uld n o t b e l o w with cs and hold l o w , or a software reset will result. cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-39
hold hold sdata serial output cs501 6 (lsb) data bus bit 0 d0 sclk serial clock data bu s bi t 1 d1 eoc en d of conversion cs501 4 (lsb) data bus bit 2 d2 eot en d of track data bu s bi t 3 d3 vd- negative digital power cs5012 (lsb) dat a bus bit 4 d4 cal calibrate data bu s bi t 5 d5 in t rlv int e rle a ve data bu s bi t 6 d6 bw bus widt h select data bu s bi t 7 d7 rst reset digital ground dgnd t st t e st p o si t iv e di g it a l p o w er vd+ va- negative a nalog pow e r data bu s bi t 8 d8 refbuf reference buffer output data bu s bi t 9 d9 vref voltage reference data bu s bi t 10 d10 agnd an a log g round data bu s bi t 11 d11 ain a nal o g input data bu s bi t 12 d12 va+ positive a nalog pow e r data bu s bi t 13 d13 bp / up bipolar/unipolar select data bu s bi t 14 d14 a0 read address (ms b ) data bus b it 15 d15 rd read clock input clkin cs chip select hold d0 sdata d1 sclk d2 eoc d3 eot d4 vd- d5 cal d6 in t rlv nc bw d7 rst dgnd t st vd+ va- nc nc d8 refbuf nc vref d9 agnd d10 ain d11 va+ d12 bp/ up d13 a0 d14 rd d15 cs clkin cs5012a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 cs5012 cs5014 cs5016 top view 18 20 22 24 26 28 1 2 4 6 4 0 4 2 44 12 8 10 14 16 7 9 11 13 15 17 29 31 33 35 37 39 34 30 32 36 38 cs5012a cs5012 cs5014 cs5016 n o te : all pin r efe r ences in this data sheet r efe r to the 40-pin di p pa c kage numbering. use this f igu r e to determin e pin numbe r s for 44-pin pa c kage. cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-40 ds14f 7
pin descriptions powe r supply connections vd+ C p ositive digital p owe r , pin 11. posit i ve digital p o wer suppl y . nominally +5 v o lts. vd- C negative digital p owe r , pin 36. n e gat i v e digital p o wer suppl y . nominally -5 v olts. dgnd C digital g r ound, pin 10. digital ground. v a+ C p osit i ve analog p owe r , pin 25. posit i ve analog p o wer suppl y . nominally +5 v olts. v a- C negat i ve analog p owe r , pin 30. n e gat i v e analog p o wer suppl y . nominally -5 v o lts. a gnd C analog g r ound, pin 27. analog ground. oscillator clkin C clock input, pin 20. all co n versions and calibrations are timed from a master clock which can either be supplied by dr i ving this pin with an e xternal clock signal, or can be internally generated by tying this pin to dgnd. digital inputs hold C hold, pin 1. a f alling transition on this pin sets the cs5012a/14/16 to the hold state and initiates a co n v ersion. this input must remain l o w at least one clkin c ycle plus 5 0 ns. cs C chip select, pin 21. when high, the data b us outputs are held in a high impedance state and the input to cal and intr l v are ignored. a f alling transition initiates or terminates b urst or interle a v e calibration (depending on the status of cal and intr l v) and a rising transition latches both the cal and intr l v inputs. if rd is l o w , the data b us is dr i ven as indicated by bw and a0. rd C read, pin 22. when rd and cs are both l o w , data is dr i v en onto the data b us. if either signal is high, the data b us outputs are held in a high impedance state. the data dr i v en onto the b us is determined by bw and a0. cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-41
a0 C read add r ess, pin 23. determines whether data or status information is placed onto the data b us. when high during the read operation, co n v erted data is placed onto the data b us; when l o w , the status r e gister is dr i v en onto the b u s. bp/ up C bipolar/unipolar input select, pin 24. when high, the d e vice is con f igured with a bipolar transfer function ranging from -vref to +vre f . encoding is in an o f fset binary format, with the mid-scale code 100...0000 centered at a gnd. when l o w , the d e vice is con f igured for a unipolar transfer function from a gnd to vre f . unipolar encoding is in straight binary format. once calibration has been performed, either bipolar or unipolar mode may be selected without the need to recalibrate. rst C reset, pin 32. when taken high for at least 10 0 ns, all internal digital logic is reset. upon being taken l o w , a full calibration sequence is initiated. bw C bus w idth select, pin 33. when hard-wired high, all 12 data bits are dr i v en onto the b us simultaneously during a data read c ycle. when l o w , the b us is in a byte wide format. on the f irst read foll o wing a co n v ersion, the eight msb s are dr i ven onto d0-d7. a second read c ycle places the four lsb s with four trailing zeros on d0-d7. subsequent reads will toggle the higher/l o wer order byte. r e gardless of bw s status, a read c ycle with a0 l o w yields the status information on d0-d7. intr l v C interle a ve, pin 34. when latched l o w using cs, the d e vice goes into interle a v e calibration mode. a full calibration will complete e v ery 2,014 co n v ersions in the cs5012a, and e very 72,051 co n versions in the cs5014/16. the e f fect i v e co n v ersion time e xtends by 20 clock c ycles. cal C calibrate, pin 35. (see addendum appending this data sheet)) when latched high using cs, b urst calibration results. the d e vice cannot perform co n versions during the calibration period which will terminate only once cal is latched l o w again. calibration picks up where the pr e vious calibration left o f f, and calibration c ycles complete e v ery 58,280 clkin c ycles in the cs5012a, and e v ery 1,441,020 clkin c ycles in the cs5014/16 . if the d e vice is co n v erting when a calibration is signaled, it will wait until that co n v ersion completes before b e ginning. analog inputs ain C analog input, pin 26. input range in the unipolar mode is zero v olts to vre f . input range in bipolar mode is -vref to +vre f . the output impedance of b u f fer dr i ving this input should be less than or equal to 20 0 w . cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-42 ds14f 7
vref C v oltage refe r ence, pin 28. the analog reference v oltage which sets the analog input range. it represents posit i ve full scale for both bipolar and unipolar operation, and its magnitude sets n e gat i v e full scale in bipolar mode. digital outputs d0 th r o ugh d15 C data bus outputs, pins 2 thru 9, 12 thru 19. 3-state output pins. enabled by cs a n d r d , t h e y o f fer t h e co n verter s o u tput in a format consistent with the state of bw if a0 is high. if a0 is l o w , bits d0-d7 o f fer status r e gister data. e o t C end of t rack, pin 37. if l o w , indicates that enough time has elapsed since the last co n v ersion for the d e vice to acquire the analog input signal. eoc C end of co n version, pin 38. this output indicates the end of a co n version or calibration c ycle. it is high during a co n v ersion and will f all to a l o w state upon completion of the co n version c ycle indicating v alid data is a v ailable at the output. returns high on the f irst subsequent read or the start of a n e w co n v ersion cycle. s d a t a C serial output, pin 40. presents each output data bit after it is determined by the success i v e approximation algorithm. v alid on the rising edge of sclk, data appears msb f irst, lsb last, and each bit remains v alid until the n e xt bit appears. sclk C serial clock output, pin 39. used to clock co n v erted output data serially from the cs5012a/14/16. serial data is stable on the rising edge of sclk. analog outputs ref b uf C refe r ence buffer output, pin 29. reference b u f fer output. a 0. 1 m f ceramic capacitor must be tied between this pin and v a-. miscellaneous tst C t est, pin 31. all o ws access to the cs5012a/14/16 s test functions which are reser v ed for f actory use. must be tied to dgnd. cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-43
parameter definitions linearity er r o r the d e viation of a code from a straight line passing through the endpoints of the transfer function after zero- and full-scale errors h a v e been accounted fo r . "zero-scale" is a point 1/2 lsb bel o w the f i rst code transition and "full-scale" is a point 1/2 lsb b e yond the code transition to all ones. the d e viation is measu r ed f r om the middl e o f e a ch p a rti c ul a r c ode. units in % full-scale. diffe r ential linearity minimum resolution for which no missing codes is guaranteed. units in bits. full scale er r or the d e viation of the last code transition from the ideal (vref-3/2 lsb s). units in lsb s. unipolar offset the d e v iati o n of the f irst code transition from the ideal (1/2 lsb ab o ve a gnd) when in unipolar mode (bp/up l o w). units in lsb s. bipolar offset the d e viation of the mid-scale transition (011...111 to 100...000) from the ideal (1/2 lsb bel o w a gnd) when in bipolar mode (bp/ up high). units in lsb s. bipolar negative full-scale er r or the d e viation of the f irst code transition from the ideal when in bipolar mode (bp/ up high). the ideal is de f i ned as lying on a straight line which passes through the f i nal and mid-scale code transitions. units in lsb s. p eak harmonic or spurious noise (mo r e accuratel y , signal to p eak harmonic or spurious noise) the ratio of the rms v alue of the signal to the rms v alue of the n e xt la r gest spectral component bel o w the nyquist rate ( e xcepting dc). this component is often an aliased harmonic when the signal frequen c y is a signi f icant proportion of the sampling rate. expressed in decibels. t o tal harmonic distortion the ratio of the rms sum of all harmonics to the rms v alue of the signal. units in percent. signal-to-noise ratio the ratio of the rms v alue of the signal to the rms sum of all other spectral components bel o w the nyquist rate ( e xcepting dc), including distortion components. expressed in decibels. a pertu r e t ime the time required after the hold command for the sampling switch to open full y . e f fect i v ely a sampling delay which can be nulled by ad v ancing the sampling signal. units in nanoseconds. a pertu r e jitter the range of v ariation in the aperture time. e f fect i v ely the "sampling wind o w" which ultimately dictates the maximum input signal sl e w r a te a c c eptable f o r a g i v e n a c c u r a c y . u nits in pi c os e conds. n o te : t empe r atu r e s speci f ied de f ine ambien t conditions in f r ee-ai r during test and do not r efe r to the junction tem p er a tu r e o f t h e devi c e . cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 2-44 ds14f 7
cs5012a o r dering guide model th r oughpu t c o n ve r sion time maximum dnl t emp . range p a c k a ge cs5012a-bp7 100 khz 7 .20 m s 1/2 lsb -4 0 to +8 5 c 40-pin plastic dip cs5012a-bl7 100 khz 7 .20 m s 1/2 lsb -4 0 to +8 5 c 44-pin plcc cs5 0 1 2 a , cs 5 01 4 , cs5 01 6 ds14f7 2-45
cs5012a, cs5014, cs5016 2 - 4 6 ds14f7 cs5014 ordering guide model throughpu t conversion time linearity temp. range package cs5014-bp14 56 khz 14.25 s 0.5 lsb -40 to +85 oc 40-pin plastic dip cs5014-bl14 56 khz 14.25 s 0.5 lsb -40 to +85 oc 44-pin plcc
cs5016 o r dering guide signal to model linearity nois e ratio co n ve r sion time t emp . range p a c kage cs5016-jp32 .0030% 87 db 32.50 m s 0 t o 7 0 c 40-pin plastic dip cs5016-jp16 .0030% 87 db 16.25 m s 0 t o 7 0 c 40-pin plastic dip CS5016-KP32 .0015% 90 db 32.50 m s 0 t o 7 0 c 40-pin plastic dip cs5016-kp16 .0015% 90 db 16.25 m s 0 t o 7 0 c 40-pin plastic dip cs5016-jl32 .0030% 87 db 32.50 m s 0 t o 7 0 c 44-pin plcc cs5016-jl16 .0030% 87 db 16.25 m s 0 t o 7 0 c 44-pin plcc cs5016-kl32 .0015% 90 db 32.50 m s 0 t o 7 0 c 44-pin plcc cs5016-kl16 .0015% 90 db 16.25 m s 0 t o 7 0 c 44-pin plcc cs5016-ap32 .0030% 87 db 32.50 m s -4 0 to +8 5 c 40-pin plastic dip cs5016-ap16 .0030% 87 db 16.25 m s -4 0 to +8 5 c 40-pin plastic dip cs5016-bp32 .0015% 90 db 32.50 m s -4 0 to +8 5 c 40-pin plastic dip cs5016-bp16 .0015% 90 db 16.25 m s -4 0 to +8 5 c 40-pin plastic dip cs5016-al32 .0030% 87 db 32.50 m s -4 0 to +8 5 c 44-pin plcc cs5016-al16 .0030% 87 db 16.25 m s -4 0 to +8 5 c 44-pin plcc cs5016-bl32 .0015% 90 db 32.50 m s -4 0 to +8 5 c 44-pin plcc cs5016-bl16 .0015% 90 db 16.25 m s -4 0 to +8 5 c 44-pin plcc cs5 0 1 2 a , cs 5 01 4 , cs5 0 1 6 ds14f7 2-47
millimeters inches dim min max min max d b a l c 13.72 51.69 1.02 0.36 0.51 3.94 3.18 0.20 0 2.41 15.24 14.22 52.71 1.65 0.56 1.02 5.08 3.81 0.38 15 0.540 2.035 0.095 0.040 0.014 0.020 0.155 0.125 0.600 0.008 0 0.560 2.075 0.065 0.022 0.040 0.200 0.150 0.015 15 40 pin plastic dip 1 40 21 20 15.87 0.625 e1 d b seating plane a b1 e1 a1 l c ea 2.67 0.105 notes: 1. positional tolerance of leads shall be within 0.25mm (0.010") at maximum material condition, in relation to seating plane and each other. 2. dimension ea to center of leads when formed parallel. 3. dimension e1 does not include mold flash. nom 13.97 52.20 1.27 0.46 0.76 4.32 - 0.25 - 2.54 - nom 0.550 2.055 0.100 0.050 0.018 0.030 0.170 - - 0.010 - a1 b1 e1 e1 ea
e e1 d1 d d2/e2 44 pin plcc no. of terminals d2/e2 max min max min millimeters inches dim a d/e 17.65 17.40 0.685 b e a a1 b e 0.695 16.66 16.51 0.650 0.656 4.57 4.20 0.180 0.165 0.53 0.33 0.021 0.013 2.29 0.090 16.00 14.99 0.590 0.630 1.19 1.35 0.047 0.053 nom 17.53 16.59 4.45 0.41 2.79 15.50 1.27 nom 0.690 0.653 0.175 0.016 0.110 0.610 0.050 3.04 0.120 d1/e1 a1
notes: 1. positional tolerance of leads shall be within 0.13mm (0.005") at maximum material condition, in relation to seating plane and each other. 2. dimension ea to center of leads when formed parallel. 40 pin cerdip 1 40 21 20 e1 d b seating plane a b1 e1 a1 l c ea 0.46 0.25 52.32 14.73 2.54 15.24 3.81 0.018 0.010 2.060 0.580 0.100 0.600 0.150 12.70 50.29 1.27 0.38 0.51 4.06 2.92 0.20 5 2.41 15.11 15.37 52.57 1.65 0.56 1.27 5.84 4.06 0.30 15 15.37 2.67 0.500 1.980 0.095 0.050 0.015 0.020 0.160 0.115 0.595 0.008 5 0.605 2.070 0.065 0.022 0.050 0.230 0.160 0.012 15 0.605 0.105 millimeters inches dim min max min e1 d e1 b1 b a1 a l ea c nom nom max
28 44 no. of terminals max min max min max min max min millimeters millimeters inches inches dim a 3.43 2.54 0.135 0.100 3.43 2.54 0.135 0.100 b 0.58 0.33 0.023 0.013 0.58 0.33 0.023 0.013 0.81 0.51 0.032 0.02 b1 0.81 0.51 0.032 0.02 d2 1 e1 top view d1 e d 28/44 pin clcc a b b1 e1 d4/e4 nom 3.05 0.46 nom 0.120 0.018 nom 3.05 0.46 nom 0.120 0.018 e2 d/e 0.660 0.640 16.26 16.76 17.78 0.700 17.27 0.680 12.19 12.70 11.18 11.68 0.480 0.500 0.440 0.460 e1 1.40 1.14 0.055 0.045 1.40 1.14 0.055 0.045 d2/e2 0.505 0.495 12.57 12.83 7.49 7.75 0.295 0.305 d4/e4 0.635 0.625 15.88 16.13 10.80 11.05 0.425 0.435 12.46 11.43 1.27 7.62 10.92 0.490 0.450 0.050 0.300 0.430 16.51 17.53 1.27 12.70 16.00 0.650 0.690 0.050 0.500 0.630 0.64 0.025 0.64 0.025 d1/e1
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